1. Technical Field of the Invention
The present invention relates in general to the field of bit-error-rate-testing, and in particular, by way of example but not limitation, to bit-error-rate-testing using statistical analysis.
2. Description of Related Art
Determination of a bit-error rate for a device under test (DUT) has many applications, including, but not limited to, testing of devices in a manufacturing context. A device under test, can be, for example, a digital communication device, system, or channel. Measurements of bit errors of a device under test typically involves inputting a sequence of bits to the device under test and comparing an output of the device to a known correct result in order to determine a number of bit errors from the device. A typical bit-error-testing system tests correct transmission through the device under test of some number of bits (N) and counts a number of incorrectly received bits (R) resulting from the transmission of the N bits.
A number of bit-error-rate-test procedures have been developed. A first such procedure involves testing of a fixed number of bits. In this procedure, N bits are chosen to test. R incorrect bits are counted. A bit-error rate estimate is then calculated as R/N. The test is considered to have been passed if R/N is less than or equal to a bit-error-rate test limit (L). The test is considered to have been failed if R/N is greater than L.
A drawback of this procedure is that there is no straightforward relationship between a value chosen for N and the accuracy of the bit-error rate estimate R/N. Rules of thumb are inevitably used to select N, which leads either to unnecessarily long test times or to a bit-error-rate estimate that is inaccurate.
A second procedure for bit-error-rate testing involves testing the device under test until a fixed number of errors have been counted. In this procedure, bits are counted until R incorrect bits are counted or until a maximal test time (T) is reached. This procedure suffers from the same disadvantages as the first procedure. Again, there is no straightforward relationship between R and T and the accuracy of the test. Rules of thumb are inevitably used to select R and T, which leads to either unnecessarily long test times or to inaccurate test results.
A third procedure for bit-error-rate testing includes density estimation and extrapolation. In this procedure, a time delay between transmission of a bit into a device under test and the bit being read out of the device under test is varied between 0 and 0.5 bit times. A number of erroneous bits at different bit time offsets is counted, which can be used to create a probability density estimate of bit-error rate as a function of offset.
The density estimate is accurate in a region near 0.5 bit time. The density estimate is extrapolated back to zero offset, which results in an estimate of the bit-error rate. A disadvantage of the third procedure is that it depends on an extrapolation of an estimated function far from where measured data is available. Accuracy is therefore suspect. In addition, it is not possible to calculate a complete density estimate quickly enough for practical applications. Therefore, various approximation methods are used, such as, for example, fitting only one mode of the density with a Gaussian. Density estimation and extrapolation methods are often used because they are called for in test standards.
Each of the procedures mentioned above has a drawback in that it is impossible to know how long to measure bit errors so as to obtain a sufficiently accurate decision about whether or not the bit-error rate is low enough. Therefore, use of any of the procedures described above often results in either unnecessarily long test times or inaccurate test results. Moreover, it is impossible to know whether the test time is too long or if the test results are inaccurate. Another drawback of the procedures described above is that the do not permit prior information regarding the bit-error rate to be taken in to account in order to minimize measurement time and maximize throughput. Another drawback of the procedures described above is that they do not provide a direct means of establishing the accuracy of the bit-error-rate testing.
There is accordingly a need for a method and system for minimal-time bit-error-rate-testing that solves these and other drawbacks associated with the prior art.
These and other deficiencies of the prior art are overcome by the present invention. In a first embodiment of the present invention, a method of performing a bit-error-rate-test is provided. This embodiment includes the steps of calculating a posterior cumulative distribution function (pcdf) of a bit-error rate based on a cumulative number of measured incorrect bits and determining whether pcdf is greater than or equal to a desired probability (C) that the bit-error rate is less than a bit-error rate test limit (L). The test is passed and stopped in response to a determination that pcdf is greater than or equal to C. If it is determined that 1xe2x88x92pcdf is greater than or equal to C, the test fails and is stopped. The test also fails and is stopped in response to a determination that the amount of time that the test is taking exceeds a maximum test time (T). The above-listed steps are repeated in response to a determination that pcdf is less than C and that 1xe2x88x92pcdf is less than C.
In another embodiment of the present invention, an article of manufacture that performs a bit-error-rate test includes at least one computer readable medium and processor instructions contained on the at least one computer readable medium. The processor instructions are configured to be readable from the at least one computer readable medium by at least one processor. The instructions cause the at least one processor to calculate a posterior cumulative distribution function (pcdf) of a bit-error rate based on a cumulative number of measured incorrect bits and determine whether pcdf is greater than or equal to a desired probability (C) that the bit-error rate is less than a bit-error-rate test limit (L).
The processor is also made to operate to designate that the test has passed and to stop the test in response to a determination that pcdf is greater than or equal to C. The processor also operates to determine whether 1xe2x88x92pcdf is greater than or equal to C and to designate that the test has failed and stop the test in response to a determination that 1xe2x88x92pcdf is greater than or equal to C. The processor also operates to designate that the test has failed and stop the test in response to a determination that the test time exceeded a maximum test time (T). The processor operates to repeat the above-listed steps in response to a determination that pcdf is less than C and that 1xe2x88x92pcdf is less than C.
In yet another embodiment of the present invention, a system adapted to perform a bit-error-rate test includes a bit-sequence generator adapted to input a bit sequence to a device under test (DUT) and a delay generator interoperably connected to the bit-sequence generator. A comparator is interoperably connected to the DUT and to the delay generator. The comparator is adapted to compare an output of the delay generator to an output of the DUT. A counter is interoperably connected to the comparator and is adapted to count an output of the comparator. The output is a cumulative number of incorrect bits.
A control computer is interoperably connected to the counter and is adapted to calculate a posterior cumulative distribution function (pcdf) of a bit-error rate based on the cumulative number of incorrect bits. The control computer also determines whether pcdf is greater than or equal to a desired probability (C) that the bit-error rate is less than a bit-error-rate test limit (L). The control computer designates whether the test passed and stops the test in response to a determination that pcdf is greater than or equal to C. The control computer determines whether 1xe2x88x92pcdf is greater than or equal to C and designates that the test has failed and stops the test in response to a determination that 1xe2x88x92pcdf is greater than or equal to C. The control computer designates that the test has failed and stops the test in response to a determination that the test time has exceeded the maximum test time (T) and also repeats the above-listed steps in response to a determination that pcdf is less than C and that 1xe2x88x92pcdf is less than C.
The above-described and other features of embodiments of the present invention are explained in detail below with reference to illustrative examples shown in the accompanying Drawings. Those of ordinary skill in the art will appreciate that the described embodiments are provided for purposes of illustration and understanding and that numerous equivalent embodiments are also contemplated in this patent application.